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Agilent HFCT-5805 155 Mb/s Single Mode Fiber Optic Transceiver for ATM, SONET OC-3/SDH STM-1
Data Sheet
Features * 1300 nm Single mode transceiver for links up to 15 Km * Compliant with T1.646-1995 Broadband ISDN and T1E1.2/98-011R1 SONET network to customer installation interface standards * Compliant with T1.105.06 SONET physical layer specifications standard * Multisourced 1 x 9 pin configuration * Interchangeable with LED multisourced 1 x 9 transceivers * Unconditionally eyesafe laser IEC 825/CDRH Class 1 compliant * Integral duplex SC connector receptacle compatible with TIA/EIA and IEC standards * Two temperature ranges: 0C - +70C HFCT-5805B/D -40C - +85C HFCT-5805A/C * Single +3.3 V power supply operation and compatible LVPECL logic interfaces * Wave solder and aqueous wash process compatible * Manufactured in an ISO 9002 certified facility * Considerable EMI margin to FCC Class B Applications * ATM 155 Mb/s links for LAN backbone switches and routers * ATM 155 Mb/s links for WAN core, edge and access switches and routers * ATM 155 Mb/s links for add/drop multiplexers and demultiplexers * SONET OC-3/SDH STM-1 (S-1.1) interconnections
Description General The HFCT-5805 transceiver is a high performance, cost effective module for serial optical data communications applications specified for a data rate of 155 Mb/s. It is designed to provide a SONET/SDH compliant link for intermediate reach links operating at +3.3 V input voltage.
ELECTRICAL SUBASSEMBLY DATA DATA POST AMPLIFIER IC PREAMPLIFIER IC OPTICAL SUBASSEMBLIES LASER DRIVER IC
PIN PHOTODIODE
SIGNAL DETECT DATA DATA
DUPLEX SC RECEPTACLE
LASER
Other Members of Agilent SC Duplex 155 Mb/s Product Family * HFCT-5801, 1300 nm single mode transceiver for links up to 15 km. The part is based on the 2 x 9 industry standard package and has laser bias, optical power monitor and transmitter disable functions. Applications Information Typical BER Performance of Receiver versus Input Optical Power Level The HFCT-5805 transceiver can be operated at Bit-Error-Rate conditions other than the required BER = 1 x 10-10 of the ATM Forum 155.52 Mb/s Physical Layer Standard. The typical trade-off of BER versus Relative Input Optical Power is shown in Figure 2. The Relative Input Optical Power in dB is referenced to the actual sensitivity of the device. For BER conditions better than 1 x 10-10, more input signal is needed (+dB).
TOP VIEW
Figure 1. Block Diagram
Transmitter Section The transmitter section of the HFCT-5805 consists of a 1300 nm InGaAsP laser in an eyesafe optical subassembly (OSA) which mates to the fiber cable. The laser OSA is driven by a custom IC which converts differential input LVPECL logic signals into an analog laser drive current. Receiver Section The receiver utilizes an InGaAs PIN photodiode mounted together with a transimpedance preamplifier IC in an OSA. This OSA is connected to a circuit providing post- amplification quantization, and optical signal detection.
Receiver Signal Detect Signal Detect is a basic fiber failure indicator. This is a single-ended LVPECL output. As the input optical power is decreased, Signal Detect will switch from high to low (deassert point) somewhere between sensitivity and the no light input level. As the input optical power is increased from very low levels, Signal Detect will switch back from low to high (assert point). The assert level will be at least 0.5 dB higher than the deassert level. Transceiver Specified for Wide Temperature Range Operation The HFCT-5805 is specified for operation over normal commercial temperature range of 0 to +70C (HFCT-5805B/D) or the extended temperature range of -40 to +85C (HFCT-5805A/C). Characterization of the parts has been performed over the ambient operating temperature range in an airflow of 2 m/s.
2
10-2 10 BIT ERROR RATIO
-3
LINEAR EXTRAPOLATION OF 10-4 THROUGH 10-7 DATA BASED ON ACTUAL DATA
10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15
-5 -4 -3 -2 -1 0
1
2
3
Figure 2. Relative Input Optical Power - dBm. Avg.
Recommended Circuit Schematic In order to ensure proper functionality of the HFCT-5805 a recommended circuit is provided in Figure 3. When designing the circuit interface, there are a few fundamental guidelines to follow. For example, in the Recommended Circuit Schematic figure the differential data lines should be treated as 50 ohm Microstrip or
stripline transmission lines. This will help to minimize the parasitic inductance and capacitance effects. Proper termination of the differential data signals will prevent reflections and ringing which would compromise the signal fidelity and generate unwanted electrical noise. Locate termination at the received signal end of the transmission line. The length of these lines should be kept short and of equal length. For the high speed signal lines, differential signals should be used, not single-ended signals, and these differential signals need to be loaded symmetrically to prevent unbalanced currents from flowing which will cause distortion in the signal. Maintain a solid, low inductance ground plane for returning signal currents to the power supply. Multilayer plane printed circuit
board is best for distribution of VCC, returning ground currents, forming transmission lines and shielding, Also, it is important to suppress noise from influencing the fiber-optic transceiver performance, especially the receiver circuit. Proper power supply filtering of VCC for this transceiver is accomplished by using the recommended, separate filter circuits shown in Figure 3 for the transmitter and receiver sections. These filter circuits suppress VCC noise over a broad frequency range, this prevents receiver sensitivity degradation due to VCC noise. It is recommended that surface-mount components be used. Use tantalum capacitors for the 10 F capacitors and monolithic, ceramic bypass capacitors for the 0.1 F capacitors. Also, it is recommended that a surfacemount coil inductor of 3.3 H be
NO INTERNAL CONNECTION TOP VIEW
NO INTERNAL CONNECTION
Rx VEER 1
RD 2
RD 3
SD 4
Rx VCCR 5
Tx VCCT 6
TD 7
TD 8
Tx VEET 9
C1 C7
C2 C8 VCC L1 L2 R2 C4 R1 C5 R4 R3 NOTES: THE SPLIT-LOAD TERMINATIONS FOR LVPECL SIGNALS NEED TO BE LOCATED AT THE INPUT OF DEVICES RECEIVING THOSE LVPECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT BOARD WITH 50 W MICROSTRIP SIGNAL PATHS BE USED. R1 = R4 = R6 = R8 = R10 = 82 W R2 = R3 = R5 = R7 = R9 = 130 W C1 = C2 = 10 F C3 = C4 = C7 = C8 = 100 nF C5 = C6 = 0.1 F L1 = L2 = 3.3 H COIL OR FERRITE INDUCTOR.
VCC TERMINATE AT PHY DEVICE INPUTS R6 R5 R7 C6 R8
C3
Vcc FILTER AT Vcc PINS TRANSCEIVER R10 R9
TERMINATION AT TRANSCEIVER INPUTS TD TD
RD
RD
SD
VCC
Figure 3. Recommended Circuit Schematic
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used. Ferrite beads can be used to replace the coil inductors when using quieter VCC supplies, but a coil inductor is recommended over a ferrite bead. All power supply components need to be placed physically next to the VCC pins of the receiver and transmitter. Use a good, uniform ground plane with a minimum number of holes to provide a lowinductance ground current return for the power supply currents. In addition to these recommendations, Agilent's Application Engineering staff is available for consulting on best layout practices with various vendors mux/demux, clock generator and clock recovery circuits. Agilent has participated in several reference design studies and is prepared to share the findings of these studies with interested customers. Contact your local Agilent sales representative to arrange for this service. Evaluation Circuit Boards Evaluation circuit boards are available from Agilent's Application Engineering staff. Contact your local Agilent sales representative to arrange for access to one if needed. Recommended Solder and Wash Process The HFCT-5805 is compatible with industry standard wave or hand solder processes. A drying cycle must be completed after wash process to remove all moisture from the module.
20.32 (0.800)
2 x O 1.9 0.1 (0.075 0.004)
20.32 (0.800)
9 x O 0.8 0.1 (0.032 0.004)
2.54 (0.100) TOP VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Figure 4. Recommended Board Layout Hole Pattern
HFCT-5805 Process Plug The HFCT-5805 transceiver is supplied with a process plug for protection of the optical ports with the Duplex SC connector receptacle. This process plug prevents contamination during wave solder and aqueous rinse as well as during handling, shipping or storage. It is made of high-temperature, molded, sealing material that will withstand +85C and a rinse pressure of 110 lb/in2. Recommended Solder Fluxes and Cleaning/Degreasing Chemicals Solder fluxes used with the HFCT-5805 fiber-optic transceiver should be water-soluble, organic solder fluxes. Some recommended
solder fluxes are Lonco 3355-11 from London Chemical West, Inc. of Burbank, CA, and 100 Flux from Alpha- metals of Jersey City, NJ. Recommended cleaning and degreasing chemicals for the HFCT-5805 are alcohol's (methyl, isopropyl, isobutyl), aliphatics (hexane, heptane) and other chemicals, such as soap solution or naphtha. Do not use partially halogenated hydrocarbons for cleaning/degreasing. Examples of chemicals to avoid are 1.1.1. trichloroethane, ketones (such as MEK), acetone, chloroform, ethyl acetate, methylene dichloride, phenol, methylene chloride or N-methylpyrolldone.
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Agilent XXXX-XXXX PROD ZZZZZ LASER
TX 21CFR(J) CLASS 1 COUNTRY OF ORIGIN YYWW RX
KEY: YYWW = DATE CODE XXXX-XXXX = HFCT-5805 ZZZZ = 1300 nm
39.6 MAX. (1.56)
12.7 (0.50)
4.7 (0.185)
25.4 MAX. (1.00)
AREA RESERVED FOR PROCESS PLUG
12.7 (0.50)
(0.010
+0.1 0.25 -0.05 +0.004 -0.002
SLOT DEPTH
2.5 (0.10)
SLOT WIDTH
2.0 0.1 (0.079 0.004)
)
9.8 MAX. (0.386) 0.51 (0.020) 20.32 (0.800) 15.8 0.15 (0.622 0.006) 2xO
3.3 0.38 (0.130 0.015) +0.25 0.46 -0.05 +0.010 -0.002
9xO
(0.018
)
(0.050
+0.25 1.27 -0.05 +0.010 -0.002
)
23.8 (0.937)
20.32 (0.800)
8 x 2.54 (0.100)
20.32 (0.800)
2xO
1.3 (0.051)
DIMENSIONS ARE IN MILLIMETERS (INCHES). TOLERANCES: X.XX 0.025mm UNLESS OTHERWISE SPECIFIED. X.X 0.05 mm
Figure 5. Package Outline Drawing and Pinout
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Regulatory Compliance The HFCT-5805 is intended to enable commercial system designers to develop equipment that complies with the various regulations governing certification of Information Technology Equipment. See the Regulatory Compliance Table 1 for details. Additional information is available from your Agilent sales representative. Electrostatic Discharge (ESD) There are two design cases in which immunity to ESD damage is important. The first case is during handling of the transceiver prior to mounting it on the circuit board. It is important to use normal ESD handling precautions for ESD sensitive devices. These precautions include using grounded wrist straps, work benches and floor mats in ESD controlled areas.
The second case to consider is static discharges to the exterior of the equipment chassis containing the transceiver parts. To the extent that the duplex SC connector is exposed to the outside of the equipment chassis it may be subject to whatever ESD system level test criteria that the equipment is intended to meet. Electromagnetic Interference (EMI) Most equipment designs utilizing these high-speed transceivers from Agilent will be required to meet the requirements of FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan. The HFCT-5805 has been characterized without a chassis enclosure to demonstrate the robustness of the part's integral shielding. Performance of a system containing these transceivers within a well designed chassis is expected to be better than the results of these tests with no chassis enclosure.
Immunity Equipment utilizing these HFCT-5805 transceivers will be subject to radio-frequency electromagnetic fields in some environments. These transceivers, with their integral shields, have been characterized without the benefit of a normal equipment chassis enclosure and the results are reported below. Performance of a system containing these transceivers within a well designed chassis is expected to be better than the results of these tests without a chassis enclosure.
Table 1. Regulatory Compliance - Typical Performance
Feature Electrostatic Discharge ESD) to the Electrical Pins Electrostatic Discharge ESD) to the Duplex SC Receptacle Electromagnetic Interference (EMI)
Test Method MII-STD-883C Method 3015.4 Variation of IEC 61000-4-2 FCC Class B
Performance Class 1 (>500 V) - Human Body Model Air discharge 15 kV
Immunity
Variation of IEC 801-3
Eye Safety
FDA CDRH 21-CFR 1040 Class 1 IEC 60825 - 1 Amendment 2 2001 - 01
Typically provide greater than 11 dB margin below 1 GHz to FCC Class B when tested in a GTEM with the transceiver mounted to a circuit card without a chassis enclosure at frequencies up to 1 GHz. Margins above 1 GHz dependent on customer board and chassis designs. Typically show no measurable effect from a 10 V/m field swept from 27 MHz to 1 GHz applied to the transceiver without a chassis enclosure. Accession Number: 9521220 - 36 License Number: 933/510031/03
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Performance Specifications Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter Storage Temperature Lead Soldering Temperature/Time Input Voltage Power Supply Voltage
Symbol TS -
Minimum -40 GND 0
Maximum +85 +260/10 VCC 4
Units C C/s V V
Notes
Operating Environment
Parameter Power Supply Voltage Ambient Operating Temperature - HFCT-5805A/C Ambient Operating Temperature - HFCT-5805B/D Symbol VCC TOP TOP Minimum +3.1 -40 0 Maximum +3.6 +85 +70 Units V C C Notes 1 1
Transmitter Section (Ambient Operating Temperature, VCC = 3.1 V to 3.6 V)
Parameter Output Center Wavelength Output Spectral Width (RMS) Average Optical Output Power Extinction Ratio Power Supply Current Output Eye Optical Rise Time Optical Fall Time Data Input Current - Low Data Input Current - High Data Input Voltage - Low Data Input Voltage - High Minimum Typical Maximum Units Notes 1261 1360 7.7 nm -15 -8 dBm 2 PO 8.2 dB ER 50 140 mA 3 ICC Compliant with Telcordia TR-NWT-000253 and ITU recommendation G.957 tR 1.5 ns 4 tF 1.7 ns 4 -200 A IIL IIH 200 A VIL - VCC -1.81 -1.475 V 5 VIH - VCC -1.165 -0.880 V 5 Symbol lce Dl
Notes: 1. 2 m/s air flow required. 2. Output power is power coupled into a single mode fiber. 3. The power supply current varies with temperature. Maximum current is specified at VCC = Maximum @ maximum temperature (not including terminations) and end of life. Typical power supply current at +25C and 3.3 V supply. 4. 10% - 90% Values. Maximum tR, t F times tested against eye mask. 5. These inputs are compatible with 10 K, 10 KH and 100 K LVPECL outputs.
7
Receiver Section (Ambient Operating Temperature, VCC = 3.1 V to 3.6 V)
Parameter Receiver Sensitivity Maximum Input Power Power Supply Current Signal Detect - Deasserted Signal Detect - Hysteresis Signal Detect Assert Time (off to on) Signal Detect Deassert Time (on to off) Signal Detect Output Voltage - Low Signal Detect Output Voltage - High Data Output Voltage - Low Data Output Voltage - High Data Output Rise Time Data Output Fall Time
Symbol ICC AS_Max ANS_Max VOL - VCC VOH - VCC VOL - VCC VOH - VCC tr tf
Minimum -7 -45 0.5 -1.84 -1.1 -1.84 -1.1 -
Typical 100 -
Maximum -31 160 -31 4 100 350 -1.6 -0.88 -1.6 -0.88 2.2 2.2
Units dBm dBm mA dBm dB s s V V V V ns ns
Notes 6 6 7
8 8 8 8 9 9
Notes 6. Sensitivity and maximum input power levels for a 2 23-1 PRBS with 72 ones and 72 zeros inserted. (ITU recommendation G.958). 7. The current includes capacitively coupled 50 Ohm terminations. 8. These outputs are compatible with 10 K, 10 KH and 100 K LVPECL outputs. 9. 20 - 80% levels.
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Table 2. Pin Out Table
Pin Symbol Mounting Studs Functional Description The mounting studs are provided for transceiver mechanical attachment to the circuit board. They are embedded in the non-conductive plastic housing and are not connected to the transceiver internal circuit. They should be soldered into plated-through holes on the printed circuit board. Receiver Signal Ground Directly connect this pin to receiver signal ground plane. Receiver Data Out Terminate this high-speed, differential, LVPECL output with standard LVPECL techniques at the follow-on device input pin. Receiver Data Out Bar Terminate this high-speed, differential, LVPECL output with standard LVPECL techniques at the follow-on device input pin. Signal Detect Normal input optical levels to the receiver result in a logic "1" output. Low input optical levels to the receiver result in a fault indication shown by a logic "0" output. Signal Detect is a single-ended, LVPECL output. This output will operate with 270 W termination resistor to VEE to achieve LVPECL output levels. This Signal Detect output can be used to drive a LVPECL input on an upstream circuit, such as, Signal Detect input and Loss of Signal-bar input. Receiver Power Supply Provide +3.3 V dc via the recommended receiver power supply filter circuit. Locate the power supply filter circuit as close as possible to the V CCR pin. Transmitter Power Supply Provide +3.3 V dc via the recommended transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the V CCT pin. Transmitter Data In Bar Terminate this high-speed, differential Transmitter Data input with standard LVPECL techniques at the transmitter input pin. Transmitter Data In Terminate this high-speed, differential Transmitter Data input with standard LVPECL techniques at the transmitter input pin. Transmitter Signal Ground Directly connect this pin to the transmitter signal ground plane.
1 2
VEER RD+
3
RD-
4
SD
5
VCCR
6
VCCT
7
TD-
8
TD+
9
VEET
Temperature Range 0C to +70C HFCT-5805B Black Case HFCT-5805D Blue Case Temperature Range -40C to +85C HFCT-5805A Black Case HFCT-5805C Blue Case
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www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. Obsoletes: 5988-2927EN September 26, 2001 5988-4255EN

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